CMOS image sensors can be manufactured by using the same manufacturing process as typical CMOS integrated circuits, and can be driven by a single power source. Hence, by further using the CMOS process, it is possible to provide the analog circuits and the logic circuits in the same chip in a mixed manner.
Thus, there are many merits such as reduction in the number of peripheral ICs.
The dominantly used output circuit of a CCD is a single channel (ch) output type which uses a FD amplifier having a floating diffusion (FD) layer.
In contrast, since the CMOS image sensor has the FD amplifier for each pixel, the dominantly used output circuit thereof is a column-parallel output type in which a single row in the pixel array is selected and the entire row is simultaneously read in the column direction.
It is difficult for the FD amplifier, which is disposed in each pixel, to exhibit a sufficient driving capability, and thus it is necessary to lower the data rate. This is a reason why parallel processing is advantageous.
FIG. 1 is a diagram illustrating an exemplary pixel of a CMOS image sensor constituted by four transistors.
The pixel 1 has a photoelectric conversion device 11 formed of, for example, a photodiode.
The pixel 1 has the following four transistors as active devices per single photoelectric conversion device 11: a transfer transistor 12, a reset transistor 13, an amplifier transistor 14, and a selection transistor 15.
The photoelectric conversion device 11 photoelectrically converts incident light into electric charges (here electrons) of which the amount corresponds to the amount of the light.
The transfer transistor 12 is connected between the photoelectric conversion device 11 and the floating diffusion FD. The transfer transistor 12 transfers electrons, which are photoelectrically converted by the photoelectric conversion device 11, to the floating diffusion FD when the gate (a transfer gate) thereof receives a drive signal through the transfer control line LTx.
The reset transistor 13 is connected between a power source line LVDD and a floating diffusion FD. The reset transistor 13 resets the electric potential of the floating diffusion FD to the electric potential of the power source line LVDD when the gate thereof receives a reset signal through the reset control line LRST.
The floating diffusion FD is connected to the gate of the amplifier transistor 14. The amplifier transistor 14 is connected to a signal line 16 through the selection transistor 15. The amplifier transistor 14 and a constant current source outside the pixel section constitute a source follower.
In addition, through the selection control line LSEL, an address signal (a select signal) can be given to the gate of the selection transistor 15. Thereby, when the selection transistor 15 is turned on, the amplifier transistor 14 amplifies the electric potential of the floating diffusion FD, and outputs the voltage corresponding to the electric potential to the signal line 16. Through the signal line 16, the voltage, which is output from each pixel, is output to the column circuit (a column processing circuit).
The reset operation of the pixel is defined as an operation of discharging electric charges, which are accumulating in the photoelectric conversion device 11, by turning on the transfer transistor 12 and transferring the electric charges accumulated in the photoelectric conversion device 11 to the floating diffusion FD.
At this time, in order to receive the electric charges of the photoelectric conversion device 11, the floating diffusion FD discharges electric charges to the power source side in advance by turning on the reset transistor 13. Alternatively, in some cases, while turning on the transfer transistor 12 is performed, in parallel with this, the reset transistor 13 is turned on, thereby directly discharging the electric charges to the power source.
This series of operations is a “pixel reset operation”.
On the other hand, in the reading operation, first by turning on the reset transistor 13, the floating diffusion FD is reset, and in this state, an output is given to the output signal line 16 through the selection transistor 15 which is turned on. This output is called a P-phase output.
Next, by turning on the transfer transistor 12, the electric charges, which are accumulated in the photoelectric conversion device 11, are transferred to the floating diffusion FD, and then the output thereof is given to the output signal line 16. This output is called a D-phase output.
The difference between the D-phase output and the P-phase output is acquired from the outside of the pixel circuit, and the reset noise of the floating diffusion FD is canceled, thereby obtaining an image signal.
This series of the operations is a “pixel reading operation”.
FIG. 2 is a diagram illustrating a typical configuration example of a CMOS image sensor (a solid-state imaging device) in which the pixels of FIG. 1 are disposed in a 2-dimensional array shape.
The CMOS image sensor 20 of FIG. 2 includes a pixel section 21 in which the pixel circuits shown in FIG. 1 are disposed in a 2-dimensional array shape, a pixel driving circuit (a vertical driving circuit) 22, and a column circuit (a column processing circuit) 23.
The pixel driving circuit 22 controls the ON/OFF states of the transfer transistors 12, the reset transistors 13, and the selection transistors 15 of the pixels in each row.
The column circuit 23 is a circuit that receives the data on the row of pixels for which the reading is controlled by the pixel driving circuit 22 and transfers the data to the signal processing circuit at the subsequent stage.
The solid-state imaging, device having such configuration has been used as an image input apparatus in various portable terminal devices, digital still cameras, digital single-lens reflex cameras, digital video cameras, and the like.
In addition, the solid-state imaging device is capable of not only the sequential reading operation but also various reading operations in accordance with the application thereof (for example, refer to JP-A-2001-298748, JP-A-2005-191814, and JP-A-2006-333035).
For example, when reading at a high speed frame is intended to be performed rather than the sequential reading of the entire pixels, the 3-row thinning-out addition reading and the like are performed.